Figure 12.1 shows an example of the operation of a BCD priority encoder. A priority encoder is a circuit that generates a binary or BCD code that corresponds to the active input with the highest priority, which generally means the activeĢ input with the highest decimal subscript. A priority encoder becomes much more complex with each additional input bit, so it is often easiest to use various VHDL constructs that describe the behavior of each circuit, rather than its specific Boolean equations. This circuit can be easily implemented in VHDL and with more difficulty in a Quartus II Block Diagram File.
Lab Reference and Equipment Required Dueck, Robert K., Digital Design with CPLD Applications and VHDL, 2/e o Chapter 6: Combinational Logic Functions 6.2 Encoders CPLD Trainer: o Altera DE1 with Altera EP2C20F484C7 CPLD Quartus II Web Edition software Experimental Notes In this lab, we will examine the behavior of a priority encoder. Test the priority encoder on a CPLD test board. Create a test circuit for the BCD priority encoder in the Quartus II Block Editor.
Write simulation criteria for the BCD priority encoder and create a simulation in Quartus II.
1 Experiment 12 Priority Encoders Objectives Upon completion of this laboratory exercise, you should be able to: Enter a VHDL design for a BCD priority encoder.
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